\doxysection{core\+\_\+cm3.\+h}
\hypertarget{core__cm3_8h_source}{}\label{core__cm3_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm3.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm3.h}}
\mbox{\hyperlink{core__cm3_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00422\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00423\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSVCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00425\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00426\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00428\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00429\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00431\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00432\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPREEMPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00434\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00435\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00437\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00438\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_ICSR\_VECTPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00440\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00441\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_RETTOBASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00443\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00444\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ SCB\_ICSR\_VECTACTIVE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00447\ \textcolor{preprocessor}{\#if\ defined\ (\_\_CM3\_REV)\ \&\&\ (\_\_CM3\_REV\ <\ 0x0201U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ core\ r2p1\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00448\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLBASE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00449\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLBASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_VTOR\_TBLBASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00451\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00452\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3FFFFFUL\ <<\ SCB\_VTOR\_TBLOFF\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00454\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00455\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFUL\ <<\ SCB\_VTOR\_TBLOFF\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00458\ \textcolor{comment}{/*\ SCB\ Application\ Interrupt\ and\ Reset\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00459\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00460\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00462\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00463\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEYSTAT\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00465\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00466\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_ENDIANESS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00468\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00469\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AIRCR\_PRIGROUP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00471\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00472\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00474\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos\ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00475\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00477\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00478\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_AIRCR\_VECTRESET\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00481\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00482\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SEVONPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00484\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00485\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00487\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00488\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPONEXIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00491\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKALIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00492\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKALIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_STKALIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00494\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00495\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00497\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00498\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DIV\_0\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00500\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00501\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_UNALIGN\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00503\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00504\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_USERSETMPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00506\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_NONBASETHRDENA\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00507\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_NONBASETHRDENA\_Msk\ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CCR\_NONBASETHRDENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00510\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00511\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00513\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00514\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00516\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00517\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00519\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Pos\ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00520\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00522\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos\ \ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00523\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00525\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos\ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00526\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00528\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Pos\ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00529\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00531\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00532\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SYSTICKACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00534\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00535\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_PENDSVACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00537\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00538\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MONITORACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00540\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00585\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00588\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00591\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00594\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00601\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00660\ \ \ \_\_IOM\ uint32\_t\ ACTLR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{00672\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISOOFP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00869\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00870\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_NUMCOMP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00872\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00873\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOTRCPKT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00875\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00876\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOEXTTRIG\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00878\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00879\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOCYCCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00881\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00882\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOPRFCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00884\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00885\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00887\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00888\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_FOLDEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00890\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00891\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_LSUEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00893\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00894\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_SLEEPEVTENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00896\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00897\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00899\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00900\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CPIEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00902\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00903\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCTRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00905\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00906\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_PCSAMPLENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00908\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00909\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_CTRL\_SYNCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00911\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00912\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00914\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00915\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTINIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00917\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00918\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTPRESET\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00920\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00921\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ DWT\_CTRL\_CYCCNTENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00923\ \textcolor{comment}{/*\ DWT\ CPI\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00924\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00925\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_CPICNT\_CPICNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00926\ }
\DoxyCodeLine{00927\ \textcolor{comment}{/*\ DWT\ Exception\ Overhead\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00928\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00929\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_EXCCNT\_EXCCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00931\ \textcolor{comment}{/*\ DWT\ Sleep\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00932\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00933\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00935\ \textcolor{comment}{/*\ DWT\ LSU\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00936\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00937\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_LSUCNT\_LSUCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00939\ \textcolor{comment}{/*\ DWT\ Folded-\/instruction\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00940\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00941\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_FOLDCNT\_FOLDCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00943\ \textcolor{comment}{/*\ DWT\ Comparator\ Mask\ Register\ Definitions\ */}}
\DoxyCodeLine{00944\ \textcolor{preprocessor}{\#define\ DWT\_MASK\_MASK\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00945\ \textcolor{preprocessor}{\#define\ DWT\_MASK\_MASK\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ DWT\_MASK\_MASK\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00947\ \textcolor{comment}{/*\ DWT\ Comparator\ Function\ Register\ Definitions\ */}}
\DoxyCodeLine{00948\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Pos\ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00949\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_MATCHED\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00951\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR1\_Pos\ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00952\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR1\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_FUNCTION\_DATAVADDR1\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00954\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR0\_Pos\ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00955\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR0\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_FUNCTION\_DATAVADDR0\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00957\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Pos\ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00958\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Msk\ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_FUNCTION\_DATAVSIZE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00960\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_LNK1ENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00961\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_LNK1ENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_LNK1ENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00963\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVMATCH\_Pos\ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00964\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVMATCH\_Msk\ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_DATAVMATCH\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00966\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_CYCMATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00967\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_CYCMATCH\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_CYCMATCH\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00969\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_EMITRANGE\_Pos\ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00970\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_EMITRANGE\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_EMITRANGE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00972\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_FUNCTION\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00973\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_FUNCTION\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ DWT\_FUNCTION\_FUNCTION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00974\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_DWT\ */}}
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\DoxyCodeLine{00988\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
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\DoxyCodeLine{00990\ \ \ \_\_IM\ \ uint32\_t\ SSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00991\ \ \ \_\_IOM\ uint32\_t\ CSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00992\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[2U];}
\DoxyCodeLine{00993\ \ \ \_\_IOM\ uint32\_t\ ACPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00994\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[55U];}
\DoxyCodeLine{00995\ \ \ \_\_IOM\ uint32\_t\ SPPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00996\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[131U];}
\DoxyCodeLine{00997\ \ \ \_\_IM\ \ uint32\_t\ FFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00998\ \ \ \_\_IOM\ uint32\_t\ FFCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00999\ \ \ \_\_IM\ \ uint32\_t\ FSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01000\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[759U];}
\DoxyCodeLine{01001\ \ \ \_\_IM\ \ uint32\_t\ TRIGGER;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01002\ \ \ \_\_IM\ \ uint32\_t\ FIFO0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01003\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01004\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01005\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01006\ \ \ \_\_IM\ \ uint32\_t\ FIFO1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01007\ \ \ \_\_IOM\ uint32\_t\ ITCTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01008\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[39U];}
\DoxyCodeLine{01009\ \ \ \_\_IOM\ uint32\_t\ CLAIMSET;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01010\ \ \ \_\_IOM\ uint32\_t\ CLAIMCLR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01011\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[8U];}
\DoxyCodeLine{01012\ \ \ \_\_IM\ \ uint32\_t\ DEVID;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01013\ \ \ \_\_IM\ \ uint32\_t\ DEVTYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01014\ \}\ \mbox{\hyperlink{struct_t_p_i___type}{TPI\_Type}};}
\DoxyCodeLine{01015\ }
\DoxyCodeLine{01016\ \textcolor{comment}{/*\ TPI\ Asynchronous\ Clock\ Prescaler\ Register\ Definitions\ */}}
\DoxyCodeLine{01017\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01018\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFUL\ }\textcolor{comment}{/*<<\ TPI\_ACPR\_PRESCALER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01019\ }
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\DoxyCodeLine{01168\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01169\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_IREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01171\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01174\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01179\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_PRIVDEFENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01198\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01205\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_XN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01206\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_XN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_XN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01208\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_AP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01211\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_TEX\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01214\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_S\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01217\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01220\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_B\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01223\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SRD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01229\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01247\ \{}
\DoxyCodeLine{01248\ \ \ \_\_IOM\ uint32\_t\ DHCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01249\ \ \ \_\_OM\ \ uint32\_t\ DCRSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{01251\ \ \ \_\_IOM\ uint32\_t\ DEMCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01252\ \}\ \mbox{\hyperlink{struct_core_debug___type}{CoreDebug\_Type}};}
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\DoxyCodeLine{01255\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_DBGKEY\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01258\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Pos\ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01365\ }
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\DoxyCodeLine{01373\ }
\DoxyCodeLine{01374\ \textcolor{comment}{/*\ Memory\ mapping\ of\ Core\ Hardware\ */}}
\DoxyCodeLine{01375\ \textcolor{preprocessor}{\#define\ SCS\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE000E000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01376\ \textcolor{preprocessor}{\#define\ ITM\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0000000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01377\ \textcolor{preprocessor}{\#define\ DWT\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0001000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01379\ \textcolor{preprocessor}{\#define\ CoreDebug\_BASE\ \ \ \ \ \ (0xE000EDF0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01380\ \textcolor{preprocessor}{\#define\ SysTick\_BASE\ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0010UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01381\ \textcolor{preprocessor}{\#define\ NVIC\_BASE\ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0100UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01382\ \textcolor{preprocessor}{\#define\ SCB\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D00UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01384\ \textcolor{preprocessor}{\#define\ SCnSCB\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCnSCB\_Type\ \ \ \ *)\ \ \ \ \ SCS\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01391\ \textcolor{preprocessor}{\#define\ CoreDebug\ \ \ \ \ \ \ \ \ \ \ ((CoreDebug\_Type\ *)\ \ \ \ \ CoreDebug\_BASE)\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01395\ \textcolor{preprocessor}{\ \ \#define\ MPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((MPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ MPU\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01396\ \textcolor{preprocessor}{\#endif}}
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\DoxyCodeLine{01402\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{01403\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Hardware\ Abstraction\ Layer}}
\DoxyCodeLine{01404\ \textcolor{comment}{\ \ Core\ Function\ Interface\ contains:}}
\DoxyCodeLine{01405\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Functions}}
\DoxyCodeLine{01406\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Functions}}
\DoxyCodeLine{01407\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Functions}}
\DoxyCodeLine{01408\ \textcolor{comment}{\ \ -\/\ Core\ Register\ Access\ Functions}}
\DoxyCodeLine{01409\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{01413\ }
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\DoxyCodeLine{01416\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ NVIC\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
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\DoxyCodeLine{01424\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_NVIC\_VIRTUAL}}
\DoxyCodeLine{01425\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{01426\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_nvic\_virtual.h"{}}}
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\DoxyCodeLine{01428\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
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\DoxyCodeLine{01430\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriorityGrouping\ \ \ \ \_\_NVIC\_SetPriorityGrouping}}
\DoxyCodeLine{01431\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriorityGrouping\ \ \ \ \_\_NVIC\_GetPriorityGrouping}}
\DoxyCodeLine{01432\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_EnableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_EnableIRQ}}
\DoxyCodeLine{01433\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetEnableIRQ\ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetEnableIRQ}}
\DoxyCodeLine{01434\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_DisableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_DisableIRQ}}
\DoxyCodeLine{01435\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPendingIRQ}}
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\DoxyCodeLine{01457\ \textcolor{comment}{/*\ The\ following\ EXC\_RETURN\ values\ are\ saved\ the\ LR\ on\ exception\ entry\ */}}
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\DoxyCodeLine{01459\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_THREAD\_MSP\ \ \ \ \ \ (0xFFFFFFF9UL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Thread\ mode,\ uses\ MSP\ after\ return\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01462\ }
\DoxyCodeLine{01472\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \_\_NVIC\_SetPriorityGrouping(uint32\_t\ PriorityGroup)}
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\DoxyCodeLine{01474\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{01475\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
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\DoxyCodeLine{01477\ \ \ reg\_value\ \ =\ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{01478\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01479\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{01480\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
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\DoxyCodeLine{01484\ }
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\DoxyCodeLine{01491\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core_debug_gae1de06155d072758b3453edb07d12459}{\_\_NVIC\_GetPriorityGrouping}}(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01493\ \ \ \textcolor{keywordflow}{return}\ ((uint32\_t)((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ >>\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}}));}
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\DoxyCodeLine{01495\ }
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\DoxyCodeLine{01503\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga71227e1376cde11eda03fcb62f1b33ea}{\_\_NVIC\_EnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
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\DoxyCodeLine{01506\ \ \ \{}
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\DoxyCodeLine{01508\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
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\DoxyCodeLine{01522\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaaeb5e7cc0eaad4e2817272e7bf742083}{\_\_NVIC\_GetEnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
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\DoxyCodeLine{01525\ \ \ \{}
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\DoxyCodeLine{01531\ \ \ \}}
\DoxyCodeLine{01532\ \}}
\DoxyCodeLine{01533\ }
\DoxyCodeLine{01534\ }
\DoxyCodeLine{01541\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae016e4c1986312044ee768806537d52f}{\_\_NVIC\_DisableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01542\ \{}
\DoxyCodeLine{01543\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01544\ \ \ \{}
\DoxyCodeLine{01545\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01546\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{01547\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{01548\ \ \ \}}
\DoxyCodeLine{01549\ \}}
\DoxyCodeLine{01550\ }
\DoxyCodeLine{01551\ }
\DoxyCodeLine{01560\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga5a92ca5fa801ad7adb92be7257ab9694}{\_\_NVIC\_GetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01561\ \{}
\DoxyCodeLine{01562\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01563\ \ \ \{}
\DoxyCodeLine{01564\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{01565\ \ \ \}}
\DoxyCodeLine{01566\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01567\ \ \ \{}
\DoxyCodeLine{01568\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{01569\ \ \ \}}
\DoxyCodeLine{01570\ \}}
\DoxyCodeLine{01571\ }
\DoxyCodeLine{01572\ }
\DoxyCodeLine{01579\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaabefdd4b790b9a7308929938c0c1e1ad}{\_\_NVIC\_SetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01580\ \{}
\DoxyCodeLine{01581\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01582\ \ \ \{}
\DoxyCodeLine{01583\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01584\ \ \ \}}
\DoxyCodeLine{01585\ \}}
\DoxyCodeLine{01586\ }
\DoxyCodeLine{01587\ }
\DoxyCodeLine{01594\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga562a86dbdf14827d0fee8fdafb04d191}{\_\_NVIC\_ClearPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01595\ \{}
\DoxyCodeLine{01596\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01597\ \ \ \{}
\DoxyCodeLine{01598\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01599\ \ \ \}}
\DoxyCodeLine{01600\ \}}
\DoxyCodeLine{01601\ }
\DoxyCodeLine{01602\ }
\DoxyCodeLine{01611\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaa2837003c28c45abf193fe5e8d27f593}{\_\_NVIC\_GetActive}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01612\ \{}
\DoxyCodeLine{01613\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01614\ \ \ \{}
\DoxyCodeLine{01615\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{01616\ \ \ \}}
\DoxyCodeLine{01617\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01618\ \ \ \{}
\DoxyCodeLine{01619\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{01620\ \ \ \}}
\DoxyCodeLine{01621\ \}}
\DoxyCodeLine{01622\ }
\DoxyCodeLine{01623\ }
\DoxyCodeLine{01633\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga505338e23563a9c074910fb14e7d45fd}{\_\_NVIC\_SetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{01634\ \{}
\DoxyCodeLine{01635\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01636\ \ \ \{}
\DoxyCodeLine{01637\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IP[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{01638\ \ \ \}}
\DoxyCodeLine{01639\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01640\ \ \ \{}
\DoxyCodeLine{01641\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHP[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{01642\ \ \ \}}
\DoxyCodeLine{01643\ \}}
\DoxyCodeLine{01644\ }
\DoxyCodeLine{01645\ }
\DoxyCodeLine{01655\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaeb9dc99c8e7700668813144261b0bc73}{\_\_NVIC\_GetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01656\ \{}
\DoxyCodeLine{01657\ }
\DoxyCodeLine{01658\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01659\ \ \ \{}
\DoxyCodeLine{01660\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IP[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{01661\ \ \ \}}
\DoxyCodeLine{01662\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01663\ \ \ \{}
\DoxyCodeLine{01664\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHP[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{01665\ \ \ \}}
\DoxyCodeLine{01666\ \}}
\DoxyCodeLine{01667\ }
\DoxyCodeLine{01668\ }
\DoxyCodeLine{01680\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gadb94ac5d892b376e4f3555ae0418ebac}{NVIC\_EncodePriority}}\ (uint32\_t\ PriorityGroup,\ uint32\_t\ PreemptPriority,\ uint32\_t\ SubPriority)}
\DoxyCodeLine{01681\ \{}
\DoxyCodeLine{01682\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01683\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{01684\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{01685\ }
\DoxyCodeLine{01686\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{01687\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{01688\ }
\DoxyCodeLine{01689\ \ \ \textcolor{keywordflow}{return}\ (}
\DoxyCodeLine{01690\ \ \ \ \ \ \ \ \ \ \ \ ((PreemptPriority\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL))\ <<\ SubPriorityBits)\ |}
\DoxyCodeLine{01691\ \ \ \ \ \ \ \ \ \ \ \ ((SubPriority\ \ \ \ \ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL)))}
\DoxyCodeLine{01692\ \ \ \ \ \ \ \ \ \ );}
\DoxyCodeLine{01693\ \}}
\DoxyCodeLine{01694\ }
\DoxyCodeLine{01695\ }
\DoxyCodeLine{01707\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga3387607fd8a1a32cccd77d2ac672dd96}{NVIC\_DecodePriority}}\ (uint32\_t\ Priority,\ uint32\_t\ PriorityGroup,\ uint32\_t*\ \textcolor{keyword}{const}\ pPreemptPriority,\ uint32\_t*\ \textcolor{keyword}{const}\ pSubPriority)}
\DoxyCodeLine{01708\ \{}
\DoxyCodeLine{01709\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01710\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{01711\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{01712\ }
\DoxyCodeLine{01713\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{01714\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{01715\ }
\DoxyCodeLine{01716\ \ \ *pPreemptPriority\ =\ (Priority\ >>\ SubPriorityBits)\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL);}
\DoxyCodeLine{01717\ \ \ *pSubPriority\ \ \ \ \ =\ (Priority\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL);}
\DoxyCodeLine{01718\ \}}
\DoxyCodeLine{01719\ }
\DoxyCodeLine{01720\ }
\DoxyCodeLine{01730\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0df355460bc1783d58f9d72ee4884208}{\_\_NVIC\_SetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ vector)}
\DoxyCodeLine{01731\ \{}
\DoxyCodeLine{01732\ \ \ uint32\_t\ vectors\ =\ (uint32\_t\ )\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{01733\ \ \ (*\ (\textcolor{keywordtype}{int}\ *)\ (vectors\ +\ ((int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET)\ *\ 4))\ =\ vector;}
\DoxyCodeLine{01734\ \ \ \textcolor{comment}{/*\ ARM\ Application\ Note\ 321\ states\ that\ the\ M3\ does\ not\ require\ the\ architectural\ barrier\ */}}
\DoxyCodeLine{01735\ \}}
\DoxyCodeLine{01736\ }
\DoxyCodeLine{01737\ }
\DoxyCodeLine{01746\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga44b665d2afb708121d9b10c76ff00ee5}{\_\_NVIC\_GetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01747\ \{}
\DoxyCodeLine{01748\ \ \ uint32\_t\ vectors\ =\ (uint32\_t\ )\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{01749\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(*\ (\textcolor{keywordtype}{int}\ *)\ (vectors\ +\ ((int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET)\ *\ 4));}
\DoxyCodeLine{01750\ \}}
\DoxyCodeLine{01751\ }
\DoxyCodeLine{01752\ }
\DoxyCodeLine{01757\ \_\_NO\_RETURN\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0d9aa2d30fa54b41eb780c16e35b676c}{\_\_NVIC\_SystemReset}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{01758\ \{}
\DoxyCodeLine{01759\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ all\ outstanding\ memory\ accesses\ included}}
\DoxyCodeLine{01760\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ buffered\ write\ are\ completed\ before\ reset\ */}}
\DoxyCodeLine{01761\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \ =\ (uint32\_t)((0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ \ \ \ |}
\DoxyCodeLine{01762\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ |}
\DoxyCodeLine{01763\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaae1181119559a5bd36e62afa373fa720}{SCB\_AIRCR\_SYSRESETREQ\_Msk}}\ \ \ \ );\ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Keep\ priority\ group\ unchanged\ */}}
\DoxyCodeLine{01764\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ completion\ of\ memory\ access\ */}}
\DoxyCodeLine{01765\ }
\DoxyCodeLine{01766\ \ \ \textcolor{keywordflow}{for}(;;)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ wait\ until\ reset\ */}}
\DoxyCodeLine{01767\ \ \ \{}
\DoxyCodeLine{01768\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
\DoxyCodeLine{01769\ \ \ \}}
\DoxyCodeLine{01770\ \}}
\DoxyCodeLine{01771\ }
\DoxyCodeLine{01773\ }
\DoxyCodeLine{01774\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ MPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01775\ }
\DoxyCodeLine{01776\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01777\ }
\DoxyCodeLine{01778\ \textcolor{preprocessor}{\#include\ "{}mpu\_armv7.h"{}}}
\DoxyCodeLine{01779\ }
\DoxyCodeLine{01780\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01781\ }
\DoxyCodeLine{01782\ }
\DoxyCodeLine{01783\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ FPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01790\ }
\DoxyCodeLine{01799\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga6bcad99ce80a0e7e4ddc6f2379081756}{SCB\_GetFPUType}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{01800\ \{}
\DoxyCodeLine{01801\ \ \ \ \ \textcolor{keywordflow}{return}\ 0U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ No\ FPU\ */}}
\DoxyCodeLine{01802\ \}}
\DoxyCodeLine{01803\ }
\DoxyCodeLine{01804\ }
\DoxyCodeLine{01806\ }
\DoxyCodeLine{01807\ }
\DoxyCodeLine{01808\ }
\DoxyCodeLine{01809\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ \ SysTick\ function\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01816\ }
\DoxyCodeLine{01817\ \textcolor{preprocessor}{\#if\ defined\ (\_\_Vendor\_SysTickConfig)\ \&\&\ (\_\_Vendor\_SysTickConfig\ ==\ 0U)}}
\DoxyCodeLine{01818\ }
\DoxyCodeLine{01830\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae4e8f0238527c69f522029b93c8e5b78}{SysTick\_Config}}(uint32\_t\ ticks)}
\DoxyCodeLine{01831\ \{}
\DoxyCodeLine{01832\ \ \ \textcolor{keywordflow}{if}\ ((ticks\ -\/\ 1UL)\ >\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga265912a7962f0e1abd170336e579b1b1}{SysTick\_LOAD\_RELOAD\_Msk}})}
\DoxyCodeLine{01833\ \ \ \{}
\DoxyCodeLine{01834\ \ \ \ \ \textcolor{keywordflow}{return}\ (1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Reload\ value\ impossible\ */}}
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